Alexandre Savard | 0a32ed7 | 2012-08-07 19:26:46 -0400 | [diff] [blame] | 1 | /* Copyright (C) 2007-2008 Jean-Marc Valin |
| 2 | * Copyright (C) 2008 Thorvald Natvig |
| 3 | * Copyright (C) 2011 Jyri Sarha, Texas Instruments |
| 4 | */ |
| 5 | /** |
| 6 | @file resample_neon.h |
| 7 | @brief Resampler functions (NEON version) |
| 8 | */ |
| 9 | /* |
| 10 | Redistribution and use in source and binary forms, with or without |
| 11 | modification, are permitted provided that the following conditions |
| 12 | are met: |
| 13 | |
| 14 | - Redistributions of source code must retain the above copyright |
| 15 | notice, this list of conditions and the following disclaimer. |
| 16 | |
| 17 | - Redistributions in binary form must reproduce the above copyright |
| 18 | notice, this list of conditions and the following disclaimer in the |
| 19 | documentation and/or other materials provided with the distribution. |
| 20 | |
| 21 | - Neither the name of the Xiph.org Foundation nor the names of its |
| 22 | contributors may be used to endorse or promote products derived from |
| 23 | this software without specific prior written permission. |
| 24 | |
| 25 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 26 | ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 27 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 28 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR |
| 29 | CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 30 | EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 31 | PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 32 | PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 33 | LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 34 | NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 35 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 36 | */ |
| 37 | |
| 38 | #include <arm_neon.h> |
| 39 | |
| 40 | #ifdef FIXED_POINT |
| 41 | static inline int32_t saturate_32bit_to_16bit(int32_t a) { |
| 42 | int32_t ret; |
| 43 | asm volatile ("vmov.s32 d24[0], %[a]\n" |
| 44 | "vqmovn.s32 d24, q12\n" |
| 45 | "vmov.s16 %[ret], d24[0]\n" |
| 46 | : [ret] "=&r" (ret) |
| 47 | : [a] "r" (a) |
| 48 | : "q12", "d24", "d25" ); |
| 49 | return ret; |
| 50 | } |
| 51 | #undef WORD2INT |
| 52 | #define WORD2INT(x) (saturate_32bit_to_16bit(x)) |
| 53 | |
| 54 | #define OVERRIDE_INNER_PRODUCT_SINGLE |
| 55 | static inline int32_t inner_product_single(const int16_t *a, const int16_t *b, unsigned int len) |
| 56 | { |
| 57 | int32_t ret; |
| 58 | uint32_t remainder = len % 16; |
| 59 | len = len - remainder; |
| 60 | |
| 61 | asm volatile (" cmp %[len], #0\n" |
| 62 | " bne 1f\n" |
| 63 | " vld1.16 {d16}, [%[a]]!\n" |
| 64 | " vld1.16 {d20}, [%[b]]!\n" |
| 65 | " subs %[remainder], %[remainder], #4\n" |
| 66 | " vmull.s16 q0, d16, d20\n" |
| 67 | " beq 5f\n" |
| 68 | " b 4f\n" |
| 69 | "1:" |
| 70 | " vld1.16 {d16, d17, d18, d19}, [%[a]]!\n" |
| 71 | " vld1.16 {d20, d21, d22, d23}, [%[b]]!\n" |
| 72 | " subs %[len], %[len], #16\n" |
| 73 | " vmull.s16 q0, d16, d20\n" |
| 74 | " vmlal.s16 q0, d17, d21\n" |
| 75 | " vmlal.s16 q0, d18, d22\n" |
| 76 | " vmlal.s16 q0, d19, d23\n" |
| 77 | " beq 3f\n" |
| 78 | "2:" |
| 79 | " vld1.16 {d16, d17, d18, d19}, [%[a]]!\n" |
| 80 | " vld1.16 {d20, d21, d22, d23}, [%[b]]!\n" |
| 81 | " subs %[len], %[len], #16\n" |
| 82 | " vmlal.s16 q0, d16, d20\n" |
| 83 | " vmlal.s16 q0, d17, d21\n" |
| 84 | " vmlal.s16 q0, d18, d22\n" |
| 85 | " vmlal.s16 q0, d19, d23\n" |
| 86 | " bne 2b\n" |
| 87 | "3:" |
| 88 | " cmp %[remainder], #0\n" |
| 89 | " beq 5f\n" |
| 90 | "4:" |
| 91 | " vld1.16 {d16}, [%[a]]!\n" |
| 92 | " vld1.16 {d20}, [%[b]]!\n" |
| 93 | " subs %[remainder], %[remainder], #4\n" |
| 94 | " vmlal.s16 q0, d16, d20\n" |
| 95 | " bne 4b\n" |
| 96 | "5:" |
| 97 | " vaddl.s32 q0, d0, d1\n" |
| 98 | " vadd.s64 d0, d0, d1\n" |
| 99 | " vqmovn.s64 d0, q0\n" |
| 100 | " vqrshrn.s32 d0, q0, #15\n" |
| 101 | " vmov.s16 %[ret], d0[0]\n" |
| 102 | : [ret] "=&r" (ret), [a] "+r" (a), [b] "+r" (b), |
| 103 | [len] "+r" (len), [remainder] "+r" (remainder) |
| 104 | : |
| 105 | : "cc", "q0", |
| 106 | "d16", "d17", "d18", "d19", |
| 107 | "d20", "d21", "d22", "d23"); |
| 108 | return ret; |
| 109 | } |
| 110 | |
| 111 | #elif defined(FLOATING_POINT) |
| 112 | |
| 113 | static inline int32_t saturate_float_to_16bit(float a) { |
| 114 | int32_t ret; |
| 115 | asm ("vmov.f32 d24[0], %[a]\n" |
| 116 | "vcvt.s32.f32 d24, d24, #15\n" |
| 117 | "vqrshrn.s32 d24, q12, #15\n" |
| 118 | "vmov.s16 %[ret], d24[0]\n" |
| 119 | : [ret] "=&r" (ret) |
| 120 | : [a] "r" (a) |
| 121 | : "q12", "d24", "d25" ); |
| 122 | return ret; |
| 123 | } |
| 124 | #undef WORD2INT |
| 125 | #define WORD2INT(x) (saturate_float_to_16bit(x)) |
| 126 | |
| 127 | #define OVERRIDE_INNER_PRODUCT_SINGLE |
| 128 | static inline float inner_product_single(const float *a, const float *b, unsigned int len) |
| 129 | { |
| 130 | float ret; |
| 131 | uint32_t remainder = len % 16; |
| 132 | len = len - remainder; |
| 133 | |
| 134 | asm volatile (" cmp %[len], #0\n" |
| 135 | " bne 1f\n" |
| 136 | " vld1.32 {q4}, [%[a]]!\n" |
| 137 | " vld1.32 {q8}, [%[b]]!\n" |
| 138 | " subs %[remainder], %[remainder], #4\n" |
| 139 | " vmul.f32 q0, q4, q8\n" |
| 140 | " beq 5f\n" |
| 141 | " b 4f\n" |
| 142 | "1:" |
| 143 | " vld1.32 {q4, q5}, [%[a]]!\n" |
| 144 | " vld1.32 {q8, q9}, [%[b]]!\n" |
| 145 | " vld1.32 {q6, q7}, [%[a]]!\n" |
| 146 | " vld1.32 {q10, q11}, [%[b]]!\n" |
| 147 | " subs %[len], %[len], #16\n" |
| 148 | " vmul.f32 q0, q4, q8\n" |
| 149 | " vmul.f32 q1, q5, q9\n" |
| 150 | " vmul.f32 q2, q6, q10\n" |
| 151 | " vmul.f32 q3, q7, q11\n" |
| 152 | " beq 3f\n" |
| 153 | "2:" |
| 154 | " vld1.32 {q4, q5}, [%[a]]!\n" |
| 155 | " vld1.32 {q8, q9}, [%[b]]!\n" |
| 156 | " vld1.32 {q6, q7}, [%[a]]!\n" |
| 157 | " vld1.32 {q10, q11}, [%[b]]!\n" |
| 158 | " subs %[len], %[len], #16\n" |
| 159 | " vmla.f32 q0, q4, q8\n" |
| 160 | " vmla.f32 q1, q5, q9\n" |
| 161 | " vmla.f32 q2, q6, q10\n" |
| 162 | " vmla.f32 q3, q7, q11\n" |
| 163 | " bne 2b\n" |
| 164 | "3:" |
| 165 | " vadd.f32 q4, q0, q1\n" |
| 166 | " vadd.f32 q5, q2, q3\n" |
| 167 | " vadd.f32 q0, q4, q5\n" |
| 168 | " cmp %[remainder], #0\n" |
| 169 | " beq 5f\n" |
| 170 | "4:" |
| 171 | " vld1.32 {q6}, [%[a]]!\n" |
| 172 | " vld1.32 {q10}, [%[b]]!\n" |
| 173 | " subs %[remainder], %[remainder], #4\n" |
| 174 | " vmla.f32 q0, q6, q10\n" |
| 175 | " bne 4b\n" |
| 176 | "5:" |
| 177 | " vadd.f32 d0, d0, d1\n" |
| 178 | " vpadd.f32 d0, d0, d0\n" |
| 179 | " vmov.f32 %[ret], d0[0]\n" |
| 180 | : [ret] "=&r" (ret), [a] "+r" (a), [b] "+r" (b), |
| 181 | [len] "+l" (len), [remainder] "+l" (remainder) |
| 182 | : |
| 183 | : "cc", "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", "q8", |
| 184 | "q9", "q10", "q11"); |
| 185 | return ret; |
| 186 | } |
| 187 | |
| 188 | #endif |